This invention relates to analog-to-digital converters (A/D converters), and in particular to dynamic element matching in multi-stage A/D converters, such as pipeline, sub-ranging, cyclic and multi-bit delta-sigma A/D converters.
The maximum achievable accuracy-speed performance of any A/D converter is limited by non-ideal effects associated with its building blocks. Typically, the performance is limited by settling time, finite amplifier gain, and/or component mismatch. When designing high-speed, high-accuracy A/D converters, these limitations impose stringent demands on building blocks, leading to prolonged design time and lower yield.
In many cases dynamic element matching can be used to reduce the negative impact of the non-ideal effects by randomizing the errors. For example, references [1-3] describe scrambling of the thermometer code bus to achieve dynamic element matching. The non-linearity of the A/D converter then appears as a random noise which increases the noise floor instead of producing harmonic distortion and intermodulation.
A problem with the prior art dynamic element matching implementations is that extra logic is required on the time critical thermometer code bus. This results in an extra signal delay, which has a negative impact on the maximal achievable sample rate.
An object of the present invention is to provide dynamic element matching for A/D converters without this extra signal delay.
This object is achieved in accordance with the attached claims.
Briefly, the present invention implements dynamic element matching outside of the thermometer code bus by forcing the comparators of the A/D sub-converter of a stage to produce a scrambled thermometer code. This eliminates the extra delay on the thermometer code bus, thereby increasing the attainable sample rate.